IPC–Association Connecting Electronics Industries and JEDEC—the Solid State Technology Association is sponsoring the 4th International Conference on Lead- Free Electronic Components and Assemblies, October 20—22, 2003 at the Hotel InterContinental Frankfurt, Frankfurt, Germany.

The European Union has officially designated 1 July 2006 as the date that the Directive on the Restriction of Hazardous Substances in Electrical and Electronic Equipment will require the majority of electronic products sold in Europe to be lead free.

Global public and political pressure against lead continues to grow. International OEMs are becoming more sensitive to the issue and continue to press their suppliers to develop phase-out plans. The European ban is having an effect in the global marketplace, forcing all manufacturers to consider lead elimination. Manufacturers in all regions, will need to prepare for this change. Companies not directly affected by the legislation, in exempted markets, still need to be monitoring this issue to assess the effects of changes in the supply chain and customer demand.

Many challenges still exist and the path forward to success is not one of consensus yet. Companies need to stay aware of the hot issues. By attending the 4th International Conference on Lead Free, IPC and JEDEC want to keep you and your company up to speed on the progress of no-lead in electronic products. IPC and JEDEC have organized both full day tutorials as well as a very strong technical conference with speakers from all over the world. Your participation by attending a tutorial or the technical conference will help your company achieve successful change by 2006.

Sponsorship Opportunities
A limited number of sponsorship opportunities are available at the IPC/JEDEC conference. If your company is interested please contact Jean Hebeisen at hebeje@ipc.org as soon as possible. Click here to download the sponsorship application (pdf).

Tabletop Exhibits
If you are interested in a tabletop exhibit, please contact Jean Hebeisen at 847-790-5338 or at hebeje@ipc.org. Click here to download the tabletop application (pdf)

Location and Hotel Information
Both the tutorials and technical conference will be held at the Hotel InterContinental Frankfurt, Wilhelm-Leuschner-Str. 43, 60329 Frankfurt am Main, Germany. Rooms are available at the hotel for a special IPC/JEDEC room rate of €165/single occupancy (includes breakfast), (approximately $182 US) per night and €175/double occupancy (approximately $192 US) (includes breakfast) per night. The GROUP Code is: Lead Free/JEDEC. For reservations, please contact the hotel at +49 69 2605 2339 or www.frankfurt.intercontinental.com. Rooms and rate are subject to availability after September 19, 2003, so please make your reservations early.

Registration Information
All educational course registrants will receive course materials, refreshments and lunch. All conference registrants will receive conference proceedings (hard copy & CD ROM), refreshments and lunch on both days. Please register by September 30, 2003. For more information, or if the registration deadline has passed, please contact IPC’s registration department at 001-847-790-5361 or e-mail registration@ipc.org. Cancellations Policy: Cancellations receive by October 17, 2003 will be refunded in full. Refunds will not be issued after the start of the program. Individuals failing to cancel will be billed for the registration fee. If events are cancelled, participants will receive a full refund. If you are unable to attend, you may send a colleague in your place.

T-01:
A Practical Guide to Lead Free Assembly & Solder Master Class
Bob Willis
Electronic Presentation Services
October 20, 2003
8:30 am—4:30 pm

This course will provide a practical guide to printed board assembly and introduce alternative lead free materials. Case studies of companies eliminating lead will be provided, along with the cost and environmental savings to be made. Each participant will take away a comprehensive handbook and an interactive CD on "Lead Free Soldering and Assembly" produced by Bob Willis and National Physics Laboratory, England worth over $150.

Attendees will be given an insight into the current position in Japan. Examples of the types of equipment and modifications to the soldering process will be discussed, as well as answers to the following questions:

• Will existing wave and reflow soldering systems cope?
• What are the technical issues relating to reflow soldering?
• Can components meet higher process temperatures?
• What design changes are necessary?
• Will the solder joints look different?
• What are the new soldering or reliability problems?
• What new process defects will be seen?

Who Will Benefit
This course is ideal for those engineers who have to look at the practical production issues associated with lead free soldering and assembly. Quality engineers responsible for analyzing the defects which have been seen with introducing higher process temperature in assembly will also benefit from this course. Technical sales engineers will be given an insight on practical issues in manufacture and how to solve them with customers.

About the Instructor
Specializing in SMT implementation, Bob Willis currently operates Electronic Presentation Services, an England-based training and consultancy business for the electronic manufacturing industry. He has worked with the GEC Technical Directorate as Surface Mount Coordinator for both the Marconi and GEC group of companies. Previously, he was Senior Process Control Engineer with Marconi Communication Systems.

T-02:
Understanding of J-STD-020B and –033A— Classification and Handling of Moisture-Sensitive ICs
Dr. Richard Shook
Agere Systems
October 20, 2003
8:30 am— 4:30 pm

Higher reflow temperatures required for lead free soldering seem are coming. Most popular alloys currently being considered as "main stream" will require processing temperatures significantly above the alloys that have been used for years by the industry. This higher temperature will have a significant impact on the component manufacturer’s qualification needs, as well as the assembler’s manufacturing process. One significant concern is the moisture sensitivity of many electronic components. IPC and JEDEC have developed two standards that address component issues. These documents are directly impacted by the lead free change.

Attendees will be provided insight into the IPC/JEDEC specification, the logic behind the requirements and the pending impacts including:

• An overview of the IPC/JEDEC moisture/reflow classification tests and their evolutionary background history.
• Moisture/reflow classification level determination for moisture-sensitive nonhermetic solid state surface mount devices (SMDs).
• Details of the new Pb-free reflow performance criteria.
• Overview of proper shipping and handling procedures for achieving safe and damage-free reflow assembly.
• Recommended baking procedures and details on extended storage using moisture "derating".
• Shelf life and dry-bag sealing requirements.
• Information and technical background details will also be discussed covering topics such as:
  • Equivalent accelerated moisture exposure
  • Proper low-humidity containment and baking procedures
  • Moisture "derating" tables
  • Desiccant science.

Who Will Benefit
Component manufacturers that want to expand their working knowledge of the IPC/JEDEC specifications. OEMs and EMS companies that want to understand the impact of higher processing temperatures on the components they use, as well as the process they use to assemble them. Material/consumable suppliers that want to understand the rating process and how it translates to requirements on the shop floor, will also benefit from this course.

About the Instructor
Rick Shook is currently a Consulting Member of Technical Staff at Agere Systems in Allentown, Pennsylvania where he is responsible for IC package development and reliability assessment. Rick has published extensively on the topic of moisture/reflow sensitivity and received an outstanding paper award at the 49th ECTC for his paper on "Handling of Highly-Moisture Sensitive Components – An Analysis of Low-Humidity Containment and Baking Schedules." He has been directly involved with US industry standardization for moisture/reflow testing through active participation on JEDEC and IPC committees. Some of Rick’s technical contributions have been the development of the accelerated 60�C/60%RH test criteria along with the addition of moisture Level 2a incorporated in the joint JEDEC/IPC moisture sensitivity specification J-STD-020, and the development of the moisture derating and baking procedures adopted in the JEDEC handling specification J-STD-033.

T-03:
Lead Free Solder Joint Reliability
Jean-Paul Clech
EPSI Inc.
October 20, 2003
8:30am—4:30pm

Solder joint reliability issues are on the critical path of lead free and mixed alloy product introduction. The problem is compounded by limited field experience, and, at times, contradictory test results. It is thus critical to gain both a fundamental and a practical understanding of what factors affect the long term reliability of lead free and mixed solder assemblies.

This workshop provides a broad coverage and a synthesis of the latest reliability information for popular lead free alloys such as Sn-Ag-Cu. The performance of lead free and mixed assemblies is put in perspective with that of Sn-Pb assemblies. Material properties and fatigue curves are presented, that explain differences in the reliability of and in the acceleration factors for SnPb and lead-free assemblies. Built upon an extensive collection of and a quantitative analysis of multi-sourced lead free reliability data, this workshop provides the necessary background and the basis for assessing the reliability risks associated with the introduction of lead-free solders in circuit board assemblies.

Topics to be Covered

• Material properties, incl. physical properties, creep data, cooling rate and composition effects: Sn-Ag, Sn-Ag-Cu
• Fatigue curves, failure modes.
• Failure distributions (shape parameters for lead-free vs. SnPb assemblies)
• Thermal cycling reliability data: 100% lead-free data (Sn-Ag-Cu), mixed assemblies (SnPb balls + lead-free paste; SAC balls + HASL); data for leadless components (LCCC, discretes), leaded packages (TSOP, QFP), BGA (PBGA, CCGA, CBGA), CSPs, Flip-Chip with & without underfill.
• Impact of components and test conditions on rank-ordering of lead-free and SnPb assembly reliability.
• Effect of component and board finish on lead-free solder joint life (thermal cycling & drop test).
• On-going developments: acceleration factors, constitutive models, life prediction models.

Who Will Benefit
Circuit board designers, packaging engineers, design, manufacturing, quality or reliability professionals and managers who are responsible for planning or implementing lead free assembly technologies in their companies’ products.

About the Instructor
Jean-Paul Clech has 18 years of practical experience in SMT quality and reliability assurance. He maintains one of the largest databases of solder joint reliability failures in the industry and is constantly challenged by problems brought about by new and emerging technologies. His current research interests are in BGA, CSP, flip-chip and lead-free assembly reliability. Jean-Paul is the founder of EPSI Inc. in Montclair, NJ. His responsibilities include technical consultation and problem solving for clients across the electronics industry and the development of engineering tools and training programs to prevent or solve reliability problems in electronics packaging and assembly.

Lead Free Electronic Components and Assemblies Registration Form
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